Part I The Lab Kit Manual
Chapter 1 Inventory
Each lab kit should contain the following items.
Section 1.1 Connectors
1 x bundle of jump wires
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Used to connect the input and output terminals to the breadboard and different components on the breadboard to each other.
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These jump wires come in four lengths about 12cm, 16cm, 20cm, & 24cm.
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You may find some jump wires with square end terminals. You cannot use these in the U of L IO Unit’s terminals, but you can use them in the breadboard.
1 x vial of short solid core wires
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To connect different components on the breadboard to each other.
2 x long solid core wires
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These wires stay inserted in the terminals at the top of the IO Unit.
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The left wire is attached to the clock.
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The right wire is attached to the probe.
1 x 9V power supply
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To connect the power in on the U of L IO Unit to a power socket.
1 x 5V power/ground cord
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To connect the power out on the U of L IO Unit to the breadboard.
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The red or striped wire is connected to the power line (+).
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The black or unstriped wire is connected to the ground line (-).
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Section 1.2 Tools
1 x chip puller
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For removing chips from the breadboard.
1 x needle nose pliers
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For straightening the pins on chips.
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Section 1.3 Electronic parts
1 x U of L IO Unit
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See the U of L IO Unit section.
1 x breadboard
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See the Breadboard section.
1 x plastic box of chips
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The chips must be securely nestled in the antistatic foam, oriented correctly (with the notch on the left), and in chip number order from left to right then top to bottom.
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See the ICs/Chips and 74LS* Reference sections.
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Chapter 2 Packing the Kit
Pack the box of chips and lab kit as follows.
Section 2.1 The Chip Set
Chips in Antistatic Foam
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Place the chips in the antistatic foam which are oriented correctly (notch on the left), and in numerical order.
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Put the foam with the chips in the chip box. Keep the ribbon lifts clear of the box.
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Drape the ribbons ends over the chips.
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Put the lid on the chip box and close the latches.
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Section 2.2 The Bottom Layer of the Lab Kit
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Place the box of chips in the bottom of the kit box with the kit label right way up.
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Coil and fasten the cord of the power supply and place it in the kit to one side of the chip box.
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Place the breadboard between the side of the kit box and the chip box.
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Place the chip puller and needle nose pliers on the opposite side of the chip box between the side of the kit box and the chip box.
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Place the vial of short wires in the corner of the kit box on the same side as the tools by the power supply.
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Section 2.3 The Middle Layer of the Lab Kit
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Coil and fasten the power/ground cord and place it on top of the power supply.
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Fasten the jump wires with the velcro wrap to form a bundle.
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Place the bundle of jump wires on top of the box of chips.
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Section 2.4 The Top Layer of the Lab Kit
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Set the U of L IO Unit on top of the power/ground cord and bundle of jump wires, face up, to prevent damage to the components.
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Put the lid on the kit box and close the latches.
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Chapter 3 The University of Lethbridge IO Unit
All the details about what the U of L IO Unit provides.
Section 3.1 General Notes
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The U of L IO Unit provides:
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Power and gounding for the breadboard
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switches and a clock for input
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LEDs and a seven segment display for output
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a probe for troublshooting
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For relative positions on the U of L IO Unit, like top, bottom, left and right:
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Find the University of Lethbridge logo. Position the U of L IO Unit so the logo reads left to right and is the right way up.
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This manual calls this standard orientation of the U of L IO Unit.
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Descriptive locations on the board are always referred to with respect to this orientation.
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Section 3.2 Power
Subsection 3.2.1 Power in
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The power in port is in the upper left corner of the UofL IO Unit.
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It is labelled 9V_In1.
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Plug the 9-volt wall plug adapter in to a standard power socket and when you are ready to test your circuit plug the other end here.
Subsection 3.2.2 Power out
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The power out port is in the upper right corner of the IO unit. It is labelled 5V_OUT1.
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Plug the 5-volt power/ground cord here.
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There are two types of The red wire or striped wire from this cable provides the 5-volts.
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The black wire or unstriped wire (marked with tape) provides ground (0 volts).
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This power cable is used to power and ground the breadboard.
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Section 3.3 Input
Subsection 3.3.1 Input Terminals & Switches
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There are 14 input terminals and associated switches.
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The input terminals are at the left side of the U of L IO Unit, at the bottom.
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The input switches are at the left side of the U of L IO Unit, in the middle.
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They are used to input data.
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The numbers under the input terminals correspond to the black numbers under the switches printed on the U of L IO Unit’s circuit board.
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Jump wires with round end caps fit in the input terminals.
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Press the button above a terminal to release the spring when putting a wire in or taking a wire out of the terminal.
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The switches are slider swithces, on is marked on the switch panels.
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Push the slider all the way to the top for on, 1, true, or closed.
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Push the slider all the way to the bottom for off, 0, false, or open.
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Subsection 3.3.2 Clock
The clock controls and terminal are found at the top of the U of L IO Unit between the power-in port and the probe switch.
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clock controls
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astable/monostable switch
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astable (up): the clock runs automatically
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monostable (down): the clock is controlled by the increment button
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increment button
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push down: for the positive edge of the clock from 0 to 1 or off to on
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release: for the negative edge of the clock from 1 to 0 or on to off
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clock terminal
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The clock terminal is labelled J4 on the U of L IO Unit.
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a long solid core wire is connected at this terminal
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attach this wire to the breadboard to use the clock you can test the clock by attaching this wire to an output terminal
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do not remove this wire
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Section 3.4 Output
Subsection 3.4.1 Output Terminals & LEDs
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There are 16 output terminals and associated LEDs.
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The output terminals are at the right side of the U of L IO Unit, at the bottom.
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The associated LEDs are on the right side of the U of L IO Unit, in the middle.
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They are used to output data.
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The numbers under the output terminals, 0, 1, 2, ..., 15 correspond to the LEDs labelled D8, D7, ...D1, D10, D11, ... D17.
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Jump wires with round end caps fit in the output terminals.
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Press the button above a terminal to release the spring when putting a wire in or taking a wire out of the terminal.
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An LED that is powered indicates on, 1, true, or high.
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An LED that is not powered indicates off, 0, false, or low.
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Subsection 3.4.2 Output Terminals & the Seven Segment Display
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Output terminals 0, 1, 2, & 3 are connected to LEDs D8, D7, D6, & D5 and the 7-segment display.
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The 7-segment display has 16 different states that correspond to the binary representation of the values from 0000 to 1111 and the hexidecimal values from 0 to F shown on the LEDs.
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Unfortunately, this unit doesn’t show the letters A to F.The table below shows the 16 states and the values they represent.
Note: the display is blank when the output value is \(1111_2 = 15_10 = F_16\text{.}\)
Subsection 3.4.3 Probe
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The probe allows you to observe signals within your design and is helpful for debugging.
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The probe is in the middle of the top edge of the IO unit, next to the clock.
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The probe slider switch turns the probe on or off.
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A long wire is connected to the probe’s terminal. Do not remove this wire from the terminal.
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The probe has a three state LED.
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If the probe wire is touching to a grounded connection (turned off/set to low/set to 0) then the light will be off.
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If the probe wire is touching a powered connection (turned on/set to high/set to 1) then the light will be on.
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If the probe wire is touching nothing or touching a connection that is neither powered nor grounded then it will blink.
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Touch the probe wire to chip pins to determine the state of inputs and outputs.
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Use the information to identify errors, broken wires, and malfunctioning chips.
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Chapter 4 The Breadboard
The solderless breadboard is the part of your kit used to connect chips to each other and to the U of L IO Unit.
Section 4.1 Description
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power and ground lines:
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A conductive metal strip is positioned horizontally under each power and ground line.
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If you have one of the new clear breadboards with the divided power and ground line then a short wire has been inserted to bridge the gap in the power and ground lines. Do not remove the bridging wires from the breadboard.
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The ground line may be above the power line or the power line may be above the ground line.
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Put the power wire of the power/ground cord in a hole at the right end of the top power line, the one next to the red line.
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Put the ground wire of the power/ground cord in a hole at the right end of the bottom ground line, the one next to the blue line.
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Conductive metal strips are positioned vertically under each column of holes above the trench and each column of holes below the strip.
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Each of the holes the above and below the trench can be identified by row letter and column number.
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The conductive metal strips do not cross the trench, so holes on opposite side of the trench are not connected.
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Section 4.2 Use
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All chips must straddle the gutter down the center of the bread board, that is, half the leads will be in row E and the other half in row F.
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The integrated circuits in your lab kit can be damaged if you switch their connections to power and ground. Therefore, we will reserve two colours of lines to help prevent this from happening.
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The top most red line is always (and only) connected to power (the red or striped wire of the power/ground cord).
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The bottom most blue line is always (and only) connected to ground (the black or plain and labelled wire of the power/ground cord).
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Chapter 5 Integrated Circuits or ICs
Section 5.1 Description
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The chips in your kit come from a standardized selection of logic parts known as the 7400 (said “seventy-four hundred”) series.
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The form of each part number is MM74FFNNP where:
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MM is a code that identifies the company that manufactured the chip.
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FF indicates the family of chips this part belongs to, in our case LS or “Advanced Low-power Schottky”) parts.
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NN indicates the logical function of the part (see 74LS* Reference).
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P is the kind of packaging used. The parts in our kit usually have “N” (for plastic, dual-inline).
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Section 5.2 Orientation
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A small notch is carved in one end of a chip to designate pin numbering, and pins are numbered counterclockwise from pin 1.
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Chips should be plugged into the board straddling the trench with the notch on the left and pin 1 in the lower left corner.
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Section 5.3 Insertion
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You should unplug the U of L IO Unit before you insert an IC.
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Use uniform pressure across the top of the IC when inserting it into the breadboard:
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This will prevent the pins from bending.
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You may have to use the needle nose pliers adjust the distance between the two rows of pins before insertion.
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Leave at least three rows of empty holes between chips so that the chip puller can fit around the chip.
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Section 5.4 Removal
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You should unplug the U of L IO Unit before you remove an IC. Always use a chip puller when removing chips from a breadboard or a socket on a printed circuit board.
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To use a chip puller:
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Place the jaws of the chip puller against the trench on either side of the chip.
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Squeeze the jaws of the chip puller until they are over the ends of the chip and the chip haas popped out of the breadboard.
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Pull straight up, evenly, to protect the pins.
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Chapter 6 74LS* Reference
For all the chips in this kit the ground is the rightmost of the pins at the bottom and the power is the leftmost of the pins at the top. The quantity of chips of each type in the kit is listed after the chip’s name in parentheses.
Section 6.1 Chips with Basic Logic Gates
Subsection 6.1.1 74LS00 Quad 2-Input NAND gates (3)
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All four NAND gates may be used independently.
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On any one gate, when either input is low the output is driven high.
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If both inputs are high the output is low.
Subsection 6.1.2 74LS02 Quad 2-Input NOR gates (1)
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All four NOR gates may be used independently.
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On any one gate, with either input high the output is low.
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When both inputs are low the output is high.
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Note: on this chip the gates are backward relative to the other gate chips.
Subsection 6.1.3 74LS04 Hex Inverter (1)
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All six inverters may be used independently.
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On any one inverter, the low-input condition drives the output high.
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The high-input condition drives the output low.
Subsection 6.1.4 74LS08 Quad 2-Input AND gates (2)
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All four AND gates may be used independently.
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On any one gate, when either input is low, the output is low.
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When both inputs are high the output is high
Subsection 6.1.5 74LS10 Triple 3-Input NAND gates (2)
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All three NAND gates may be used independently.
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On any one gate, when any input is low, the output is driven to a high state.
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When all three inputs are high, the output is driven to a low state
Subsection 6.1.6 74LS11 Triple 3-Input AND gates (1)
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All three AND gates may be used independently.
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On any one gate, when any input is low, the output is driven to a low state.
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When all three inputs are high, the output is driven to a high state.
Subsection 6.1.7 74LS20 Dual 4-Input NAND gates (2)
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Both 4-input gates may be used independently.
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On either gate, any input-low condition drives the out- put high.
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When all inputs are high, the output is low.
Subsection 6.1.8 74LS21 Dual 4-Input AND gates (1)
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Both 4-input gates may be used independently.
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On either gate, any input-low condition drives the out- put low.
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When all inputs are high, the output is high.
Subsection 6.1.9 74LS27 Triple 3-Input NOR gates (1)
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All three NOR gates may be used independently.
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On any one gate, when any input is high, the output is driven to a low state.
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When all three inputs are low, the output is driven to a high state
Subsection 6.1.10 74LS32 Quad 2-Input OR gates (1)
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All four OR gates may be used independently.
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On any one gate, when either input is high, the output is driven high.
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When both inputs are low the output is low.
Subsection 6.1.11 74LS86 Quad Exclusive-OR gates (2)
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All four XOR gates may be used independently.
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On any one gate, when one, but not both, inputs are high, the output is high.
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When both inputs are high or both inputs are low, the output is low.
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Section 6.2 Chips with complex functions
Subsection 6.2.1 74LS139 Dual 2→4 Decoder (1)
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The chip contains two individual decoders.
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Each decoder drives one line according to the binary value at its address.
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This circuit can also be used to make a 3→8 decoder.
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Suppose we have inputs \(I\text{,}\) \(J\text{,}\) and \(K\text{.}\)
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Connect \(I\) to \(\overline{E_1}\) and connect \(I\) to \(\overline{E_2}\) using an inverter.
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Connect \(J\) to both \(A_1\) and \(A_2\text{.}\)
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Connect \(K\) to both \(B_1\) and \(B_2\text{.}\)
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| Enable | \(A_iB_i\) | \(X_0/Y_0\) | \(X_1/Y_1\) | \(X_2/Y_2\) | \(X_3/Y_3\) |
| 0 | 00 | 0 | 1 | 1 | 1 |
| 0 | 00 | 1 | 0 | 1 | 1 |
| 0 | 00 | 1 | 1 | 0 | 1 |
| 0 | 00 | 1 | 1 | 1 | 0 |
| 1 | XX | 1 | 1 | 1 | 1 |
Subsection 6.2.2 74LS157 Quad 1-of-2 Multiplexer (2)
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This device selects (SELECT) between two inputs (A and B) to drive the output (OUT).
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All four of the switches are simultaneously enabled or selected.
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If the Enable input is high, all outputs will be low.
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Otherwise, the Select determines whether the A or B inputs control the output.
Subsection 6.2.3 74LS175 Quad "D" Memory (2)
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Four bits of memory are stored in four separate positive-edge triggered D-type flip-flops, each with normal, Q, and complementary, Q, output.
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Information at the D inputs is entered in all 4 bits of memory simultaneously on the positive edge of the clock.
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The Clear input is normally held high, bringing it to ground will clear the memory, making all Q outputs low.
Subsection 6.2.4 74LS283 4-Bit Full Adder (1)
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This is an arithmetic unit that provides the sum of two 4-bit binary numbers and an input carry C0 as follows:
Subsection 6.2.5 74LS670 4x4 Register File (1)
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The register file is organized as four 4-bit locations.
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The independent \(\overline{\text{Enable}}\) and addresses for read and write permits simultaneous writing into one location and reading from another location.
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The outputs are Read 1, 2, 3, 4.
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The inputs are Write 1, 2, 3, 4; Read Address AB; Write Address AB; Write \(\overline{\text{Enable}}\text{;}\) and Read \(\overline{\text{Enable}}\text{.}\)
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To save 1101 to memory location 2
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Set the write \(\overline{\text{Enable}}\) to 1, the read \(\overline{\text{Enable}}\) to 0.
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Set the read and write addresses AB=10.
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Set Write 1, 2, 3, 4 to 1101.
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Change the write \(\overline{\text{Enable}}\) to 0, pause, then set it to 0.
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To read memory location 1
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Set the write \(\overline{\text{Enable}}\) to 1, the read \(\overline{\text{Enable}}\) to 0.
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Set the read addresses AB=01.
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The contents of the memory will be displayed by Read 1, 2, 3, 4.
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